RISC-V Architecture and DSP Processor Design. Design and implement a high-performance RISC-V DSP core from ISA to SoC Zhang Zhiwei

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Autor:: Zhang Zhiwei
Wydawnictwo:: Packt Publishing (Z chęcią przeczytam książkę w języku polskim)
Ocena:: Bądź pierwszym, który oceni tę książkę
Stron:: 280
Dostępne formaty:: PDF

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RISC-V is reshaping processor innovation with its open and extensible instruction set architecture. But how are high-performance RISC-V digital signal processors (DSPs) designed in practice? This book explores that question through SpringCore, a RISC-V DSP architecture developed for real-time embedded control systems.
Using SpringCore as a case study, the book introduces the architecture of a modern DSP processor and explains key digital design techniques used in its implementation. You will explore DSP architecture concepts, design custom ISA extensions for fixed-point and floating-point acceleration, and examine an 8-stage pipelined processor with hazard handling, zero-overhead loops, a Harvard memory architecture, protection mechanisms, and interrupt handling. The book also covers the surrounding software ecosystem, including an LLVM-based toolchain, debugging with OpenOCD and JTAG, development with an Eclipse-based IDE, and simulation support using tools such as gem5. Finally, it demonstrates how the SpringCore architecture is implemented in the FDM320RV335 DSP chip, which runs at 150 MHz and integrates peripherals such as an ADC and PWM for real-time industrial control.
By the end, you will understand key DSP hardware architecture and custom ISA design principles through the practical example of SpringCore.

O autorze książki

Zhang Zhiwei is a Ph.D., Researcher, and Doctoral Supervisor at the Institute of Automation, Chinese Academy of Sciences (CAS). He serves as Deputy Director of the National Engineering Research Center for Specialized IC Design and leads the Digital Signal Processor research group. With nearly 20 years of experience in DSP architecture and chip development, he has led more than 10 national-level semiconductor projects. His expertise spans DSP microarchitecture, high-performance processor design, and physical implementation, with multiple products deployed at scale.

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Szczegóły książki

Tytuł oryginału:: RISC-V Architecture and DSP Processor Design. Design and implement a high-performance RISC-V DSP core from ISA to SoC
ISBN Ebooka:: 978-18-076-0088-4, 9781807600884
Data wydania ebooka :: 2026-04-30 Data wydania ebooka często jest dniem wprowadzenia tytułu do sprzedaży i może nie być równoznaczna z datą wydania książki papierowej. Dodatkowe informacje możesz znaleźć w darmowym fragmencie. Jeśli masz wątpliwości skontaktuj się z nami sklep@helion.pl.
Język publikacji:: angielski
Rozmiar pliku Pdf:: 29.6MB
Rozmiar pliku ePub:: 29.5MB